Overview

Currently, the state of the art for embedded processors are System-on-a-Chip (SoC) architectures. They are tailored for a specific application. But very often number of required integrated circuits (IC) does not allow the fabrication of a specialized IC. Configurable Systems-on-a-Chip combine standard components with a reconfigurable (FPGA) part. Using this reconfigurable part it is now possible to dynamically adapt the hardware to the requirements of the running application. For this main goal we developed the AMIDAR-class of reconfigurable processors. AMIDAR stands for Adaptive Microinstruction Driven Architecture.

The main goals for architectures derived from the AMIDAR model are:

• Optimization of performance,
• Optimization of power consumption, and
• Optimization of realtime behaviour.

Until now the most important parts of the AMIDAR Model are clearly defined. We derived the architecture of an adaptive Java bytecode processor from the model and implemented it in a simulator. The simulation results show the feasibility of the concept and also the benefits of a dynamic adaption to the requirements of some sample applications.

Currently we are testing an implementation of a thread scheduler. Also an exception Handler is being developed.

The figure shows the basic structure of an adaptive processor. It consists of four main types of components: a token generator, functional units (FU), a token distribution network and a communication structure. The token generator receives instructions and generates tokens for the functional units. The tokens describe, what the functional units have to do to accomplish the execution of the original instruction. The tokens are distributed over the token distribution network in parallel, the required data for the functional units over the communication structure. Because the tokens can be seen as micro instructions and the tokens trigger the functional units, we call our architecture a micro instruction driven architecture.

There are several research topics which are subject of our investigations:

• The development of different Architectures using the AMIDAR model.
• The Runtime Analysis to collect statistics about bottlenecks inside functional units or the communication structure.
• The elaboration of Heuristics for a meaningful reconfiguration of the AMIDAR processor.
• The development of tools and algorithms for a dynamic Synthesis inside the AMIDAR processor.
• The development of other Sample Implementations that are suitable for the AMIDAR working principle.