Detailed explaination of AMIDAR processors
This paper contains the original idea of AMIDAR. A brief description of the most current implementation in hardware on an FPGA containing a hardware debugger can be found
here.
Differences are for example the implementation of a Framestack (instead of separate Functional Units for Method Stack and Local Variable Memory) and additions like Garbage Collector or a periphery model.
Online Synthesis of CGRA-based Accelerators:
In this paper the basic principle of all synthesis steps including online profiling, CDFG generation and scheduling is described.
Recent work concentrates on the optimization of these synthesis steps. Important changes are that the CGRA now can access the memory directly via DMA and the implementation of speculative method inlining. Detailed information can be found in
The scheduler and the current CGRA architecture can be found in
The communication between AMIDAR and the CGRA is still beeing optimized. The current state is described in